In networking systems, routers and/or switches typically use lookup tables to facilitate or increase the speed of the forwarding of packets of information. Such tables can be implemented in hardware, for example, as content-addressable memory (CAM), which can include static random access memory (SRAM) type memory cells. Among the types of forwarding that can be accommodated in typical systems are layer 2 (L2) and/or layer 3 (L3) forwarding. L2 tables can include Media Access Control (MAC) and L3 tables can include Internet Protocol (IP). Other example table types include IP MultiCast (MC), IP Next Hop Table (NHT), and IP Longest Prefix Match (LPM) tables. Internal (i.e., on-chip) tables can be used for the L2/L3 forwarding and these tables can be modified by hardware and/or software. However, because such tables may typically be integrated on a single chip to allow for line rate lookups, there are practical limitations as to the possible sizes of the tables. These limitations include practical die size factors that limit the number of lookup table entries that can be stored on-chip.
One possible solution is to locate the lookup tables externally (i.e. off-chip), but this arrangement may still suffer from limited size and/or lack of flexibility in making the most efficient use of the available memory. Another possible solution is to extend each of the internal tables to also use external memory. Such a conventional system structure is shown in FIG. 1 and indicated by the general reference character 100. In FIG. 1, Router/Switch 102 includes Forwarding Engine 104, External IP Table Interface 106, and External MAC Table Interface 108. The IP table can be extended to include IP Table External Memory 110. Similarly, the MAC table can be extended to include MAC Table External Memory 112. However, drawbacks of this conventional approach include increased system costs due to likely back-end board area increases, primarily due to more pins needed on the package to support multiple external memory interfaces. Further, such conventional approaches typically do not support flexible allocation of the external memory. Accordingly, chips may have inadequate or limited IP table and/or MAC table entries for many applications. Further, this approach may be limited by physical memory and associated interface limitations, such as the refresh rate requirement of dynamic (e.g., DRAM). Overall, negatives such as an increased number of pins on the package due to supporting multiple interfaces drives up the cost of the system and, along with a lack of flexible allocation, makes this approach undesirable.
Consequently, what is needed is a solution that can flexibly allocate external memory and can effectively extend internal lookup tables without using multiple, relatively costly, memory interfaces.